1. Field of the Invention
The present invention relates to a cooling system for a semiconductor device and a method of fabricating same and, more particularly, to a cooling system including backside trenches and a method of fabricating same.
2. Description of the Related Art
The advent of nanotechnology has resulted in an exponential growth of integrated circuit density. The increasingly dense integrated circuits generate more thermal heat than past circuits. However, many known passive or active semiconductor cooling systems are incapable of adequately dissipating excessive amounts of thermal heat.
In addition, the increase of wafer thickness due, in part, to the use of an extra oxide layer as a result of silicon-on-insulator (SOI) technology, will require more sophisticated cooling systems. In order to compensate for additional thermal resistance on the backside of the wafer, these cooling systems can be placed as close to the chip as possible.
Embedded cooling devices on integrated-circuit chips are known. See, e.g., U.S. Pat. No. 5,313,094 to Beyer et al. Some of the known embedded cooling devices provide heat dissipation by etching a trench or hole through an active silicon region and an underlying dielectric layer to a supportive silicon substrate, oxidizing a trench wall, and filling the trench with a material having high thermal-conductivity, such as CVD diamond.
Integrated-circuit chips with full trench dielectric isolation of each portion of the chip are also known. See, e.g., U.S. Pat. Nos. 5,753,529, 5,757,081 and 5,767,578 to Chang et al. After etching trenches in a substrate and filling the trenches with dielectric material, a heat sink cap is attached to a passivation layer on the front side of the substrate. The passivation layer can be made of conventional material such as plasma nitride or a CVD diamond film that provides both electrical insulation and thermal conductivity.
Trenches formed from the top of a bonded SOI wafer through an isolation layer to a base layer are also known. See, e.g., U.S. Pat. No. 6,080,608 to Nowak. A conductive pillar in a trench may be formed of doped polysilicon, which provides a heat sink that is physically in contact with, but electrically insulated from, the base of the SOI wafer.
Known methods of forming conventional cooling devices in integrated circuits require that deep trenches be etched, in the final steps of the manufacturing process, from the front side of a wafer, through metal interconnect and device levels, to the bottom of the wafer. The trenches are filled with thermally conductive material to help dissipate the heat generated by the chip. The etching of deep trenches from the front side of the wafer, however, has a number of drawbacks. For example, front-side trench etching results in increased chip area and reduced circuit density. In order to position thermal trenches in an area that generates the most thermal power, existing circuits must be moved to a less congested area and die size needs to be increased. Another problem with front-side trench etching is that the trench must be relatively small due to the area constraints and deep enough to extend from the front side to the backside of a chip. As a result, the processing of small and deep trenches is time consuming and expensive.
Front-side trench etching also can degrade device reliability. Due to the close proximity of trenches to semiconductor devices on a chip, undesirable crystalline defects, such as dislocations, may result from mechanical stress caused during the fabrication of a trench. Further, front-side trench etching may compromise the quality of a metal interconnect. The etching of deep trenches through metal interconnect levels may force some metal wires to change their routing path and may reduce the density of the metal interconnects.
Therefore, there exists a need for a different approach to trench construction which eliminates the problems that arise from front-side trench etching.